SLVSELI=NOT_SET, TFORI=NOT_SET, MDFI=NOT_SET, SREI=NOT_SET, TFRQI=NOT_SET, RFORI=NOT_SET, DBGMD=RUN, TFILI=NOT_SET, URI=NOT_SET, BUSYF=NOT_SET, NSSSTS=LOW, RFRQI=NOT_SET, RFILI=NOT_SET
Module Control
| RFRQI | Receive FIFO Read Request Interrupt Flag. 0 (NOT_SET): The RX FIFO has fewer bytes than the level defined by RFTH. 1 (SET): The RX FIFO has equal or more bytes than the level defined by RFTH. |
| RFORI | Receive FIFO Overrun Interrupt Flag. 0 (NOT_SET): Read: A receive FIFO overrun has not occurred. Write: Clear the flag. 1 (SET): Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt. |
| TFRQI | Transmit FIFO Write Request Interrupt Flag. 0 (NOT_SET): The TX FIFO has fewer empty slots than the level defined by TFTH. 1 (SET): The TX FIFO has at least as many empty slots as the level defined by TFTH. |
| TFORI | Transmit FIFO Overrun Interrupt Flag. 0 (NOT_SET): Read: A transmit FIFO overrun has not occurred. Write: Clear the flag. 1 (SET): Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt. |
| SLVSELI | Slave Selected Interrupt Flag. 0 (NOT_SET): The slave select signal (NSS) is not active. 1 (SET): The slave select signal (NSS) is active. |
| MDFI | Mode Fault Interrupt Flag. 0 (NOT_SET): Read: A master mode collision is not detected. Write: Clear the flag. 1 (SET): Read: A master mode collision occurred. Write: Force a mode fault interrupt. |
| URI | Underrun Interrupt Flag. 0 (NOT_SET): Read: A data transfer is still in progress. Write: Clear the flag. 1 (SET): Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt. |
| SREI | Shift Register Empty Interrupt Flag. 0 (NOT_SET): There is data still present in the transmit FIFO or shift register. 1 (SET): All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO. |
| RFILI | Illegal Receive FIFO Access Interrupt Flag. 0 (NOT_SET): Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag. 1 (SET): Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt. |
| TFILI | Illegal Transmit FIFO Access Interrupt Flag. 0 (NOT_SET): Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag. 1 (SET): Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt. |
| NSSSTS | NSS Instantaneous Pin Status. 0 (LOW): NSS is currently a logic low. 1 (HIGH): NSS is currently a logic high. |
| BUSYF | SPI Busy. 0 (NOT_SET): The SPI is not busy and a transfer is not in progress. 1 (SET): The SPI is currently busy and a transfer is in progress. |
| RFCNT | Receive FIFO Counter. |
| TFCNT | Transmit FIFO Counter. |
| DBGMD | SPI Debug Mode. 0 (RUN): The SPI module will continue to operate while the core is halted in debug mode. 1 (HALT): A debug breakpoint will cause the SPI module to halt. |